演講大綱/摘要:

1. Introduction to Package
2. Micron Packaging Sites
3. Package Trend

國立中央大學 周景揚校長將與各位分享

「每個人都是一本小說」

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聯詠科技iVoT產品事業處 王裕閔 副處長將與各位分享

「Applications of Edge Intelligence Vision Device」

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大麥影像傳播工作室 麥覺明導演將與各位分享

「人生風景無限 一條路 走就對了」

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展碁國際 林佳璋總經理將與各位分享

「談新鮮人如何建構未來競爭力」

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Heterogeneous integration poses new challenges to electronic design automation (EDA) and packaging communities and demands innovative solutions that must be built together with tight-knit collaborations. One key outcome is the EDA-enabled benchmarking capability that provides quantified evaluation of manufacturing technologies under development using system-level design metrics of interest. We present two such examples, first on glass vs. silicon as the interposer material choices, and second on hybrid bonding vs. micro bumping as the die bonding options, both targeting system-level power, performance, area, and cost (PPAC) optimization. In addition, thermal, power delivery, and other reliability related metrics are calculated and compared. Lastly, we discuss various algorithms and methodologies developed to enable these EDA tools that are based on conventional and AI approaches.

Logic synthesis, as an essential step in the VLSI design automation flow, has been developed with the characteristics of CMOS digital circuits in mind. However, with the increasing demand for computationally-heavy applications, researchers have been investigating various beyond-CMOS technologies featuring faster computation speed and/or lower energy consumption. These emerging technologies often have distinct characteristics and constraints to be taken into account in logic synthesis. For example, some technologies are based on majority gates, instead of NAND gates; some technologies have pathbalancing and fanout constraints; and some technologies require a planar circuit layout, where wire crossings also need to be balanced. In this talk, I will discuss how modern logic synthesis techniques may be applied to, or adapted for, beyond-CMOS technologies with special characteristics.

中科院前院長 杲中興院長將與各位分享

「從IDF數控飛操系統開發經驗談技術轉移的陷阱」

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奇景光電-徐正池資深處長 將與各位分享

「車載顯示IC技術發展」

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Speaker: Prof. Shimeng Yu (Georgia Institute of Technology)

Topic: Recent Progresses of Compute-in-Memory Prototype Chips: RRAM, 3D integration and Ferroelectric Technologies

Abstract:

In this presentation, we will present the recent progresses on the compute-in-memory (CIM) prototype chips. Mixed-signal resistive random access memory (RRAM) based CIM can process the multiply-accumulate (MAC) functions in deep neural networks efficiently, thus it is regarded as a competitive solution for AI hardware design for edge intelligence. We recently taped out two generations of RRAM CIM macros in TSMC  40 nm process. The following features are supported in these macros: 1) Adaptive input sparsity control; 2) Reconfigurable weight precision; 3) Integrated digital compute units; 4) Input-aware on-chip ADC reference; 5) On-chip write-verify controller; 6) Input encoding for embedded security; 7) ADC-less communication between sub-arrays with pulse-width-modulation; 8) In-situ error correction code that preserves the MAC parallelism.  We will introduce these design techniques and silicon measurement results. Next the prospects and challenges of CIM chip design will be discussed. Leveraging the advanced packaging techniques, 3D physical design partition and 3D processing-element (PE) cube design is proposed to scale the RRAM CIM macro with digital PE for larger neural network (e.g., vision transformer). Assembly of many 3D PE cubes in a 2.5D integrated silicon interposer could potentially extend the support for large language model (e.g., GPT). Finally, switching the technology from RRAM to ferroelectric devices could further improve the energy efficiency due to the reduced static power via charge-domain computing.

Bio:

Shimeng Yu is a full professor of electrical and computer engineering at Georgia Institute of Technology. He received the Ph.D. degree in electrical engineering from Stanford University in 2013. From 2013 to 2018, he was an assistant professor at Arizona State University. Prof. Yu’s research expertise is on the emerging non-volatile memories for applications such as deep learning accelerator, in-memory computing, and 3D integration.  Prof. Yu currently serves technical program committee for the IEEE Symposium on VLSI Technology and Circuits, and also serves an editor for IEEE Electron Device Letters (EDL). He is a senior member of the IEEE.

報名連結： https://forms.gle/PS5ZuQrwAYp5JNKN8

主辦單位：臺大電子所

協辦單位：臺灣大學重點科技研究學院 / 聯發科技-臺大創新研究中心/ 臺大SOC中心

演講聯絡人:

臺大電子所專任助理

邱玉霜 Susan Chiou

yuhshuang@ntu.edu.tw

02-33663718

台北市羅斯福路四段一號電機二館308室

演講大綱/摘要:

介紹臺大圖書館豐富館藏資源與服務，並說明參考文獻類型與查詢途徑及技巧、引用文獻資料庫（Web of Science與Scopus）與IEEE Xplore、引文格式與書目管理軟體、Open Access 與獲取文獻全文方法等，有助於提升研究生的資訊素養，讓課業學習與論文寫作更加順遂。

本次活動有興趣可至連結報名：https://forms.gle/55RzzDH5gAN36JBV9

演講大綱﹕

The use of millimeter-wave communications in 5G radios becomes viable if extensive beamforming is employed to overcome the high path loss and the power consumption is sufficiently low to afford frequent high-throughput connections for mobile devices. Recent beamforming receivers in the vicinity of 28 GHz draw, per element, 28 mW to 50 mW. Moreover, most reported receivers do not include complete on-chip LO synthesis.

A key observation in the design of beamforming receivers is that the phase shift network typically consumes high power whether it appears in the RF path or the LO path. This presentation introduces a new technique that avoids the bandwidth-loss-phase shift tradeoffs of conventional topologies. In addition, several other new concepts are offered that reduce the power with no noise figure penalty. Fabricated in TSMC’s 28-nm CMOS technology, the eight-element prototype draws 166 mW, achieving a minimum noise figure of 3.7 dB, a phase resolution of 11.7 degrees,and an LO jitter of 155 fs.

作者簡介﹕

Behzad Razavi is Professor of Electrical Engineering at UCLA, where he conducts research on analog and RF integrated circuits. Prof. Razavi has served as an IEEE Distinguished Lecturer and published more than 200 papers and eight books. He has received nine IEEE best paper awards and six teaching and education awards, and his books have been published in seven languages. He received the IEEE Pederson Award in Solid-State Circuits and was recognized as one of the top ten authors in the 50-year history of the IEEE International Solid-State Circuits Conference. He is a member of the US National Academy of Engineering and a fellow of the US National Academy of Inventors.

瓦雷科技-項春申創辦人 將與各位分享

「Business Sense for Engineers」

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演講大綱/摘要:

1.固態存儲市場介紹

2.固態存儲技術發展

聯發科技-張湘輝資深處長 將與各位分享

「AI for radio system solution」

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Abstract

I will introduce the fast-growing sport (esp. baseball) industry that is being populated and renovated by emerging semiconductor and AI technologies. The sport industry is much larger than the semiconductor industry itself. Development of sport technology requires cross-disciplinary research and education in the sport domain and the technology side, i.e., in addition to the domain knowledge in sport science, we need to integrate technologies in IOT, AI, 5G, cloud computing, advanced sensors, etc. Trends in areas like smart venue, immersive media, quantified athlete, real-time online streaming, fan engagement, etc., will be introduced. Examples of existing products, systems, and services powered by semiconductors will be given.

演講大綱/摘要:

1. 微型機器學習(TinyML)趨勢
2. 超低功耗機器學習晶片設計挑戰
3. 奇景光電解決方案與應用案例分享

 綠夾克運動事業(Golface)-廖聰哲執行長將與各位分享

「從Golface聊創業、⼯作與求學」

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台積電-吳志強處長 將與各位分享

「Expanding Role of TCAD in TSMC R&D」

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演講大綱/摘要:
隨著半導體科技的飛速成長，運算平台的基礎架構，從 Bit 為主導的數位運算，已進入 Neurons 所啟發的人工智慧運算。在此將會探討IC半導體的進展，如何影響AI的興起，並討論各種AI算力的技術演進。

AI 的神經網路架構，近幾年有很大的進展。神經網路的參數數目，快速由2012年的千萬規模，現今進入千億規模，而有些研究已經開始探討接近人腦的千兆規模。因為大型語言神經網路模型 (Large Language Model，簡稱LLM) 的成熟，衍生許多令人驚豔的全新應用。最近對話式AI - ChatGPT的崛起，短短兩個月內吸引上億使用者，讓全世界都深刻的感受到 AI 的浪潮。而與 LLM結合的生成式AI (Generative AI)，可透過文字描述，產生高品質的影像、影片、音樂甚或程式設計，AI對生產力的提升，具有極大的潛能，可能顛覆人類未來的工作與生活模式。

但是，要讓大型神經網路的 AI能力湧現 (Emergence) ，需要極大量的運算需求，短短三年間成長數十萬倍以上，遠超過半導體摩爾定律的成長速度，極大量的AI運算需求，也帶來半導體的新機會。為了提供算力，百億億級AI 超級電腦 (Exascale AI Supercomputer) 需求殷切，在此也會討論世界超級電腦的進展。此外，大型神經網路的訓練，也十分重要。若訓練語料中隱含著偏見或毒化的資訊，會讓AI模型的瑕疵，影響到所有任務。因此AI 模型的安全性，也成為新的資安議題。也因此，台灣應該也要有自身訓練大型神經網路的能力與技術，在AI 發展上有更大的主導權。

AI的運算需求，將成為AI進展與普及的關鍵。台灣身處半導體產業鏈的關鍵角色，除了應該思考由IC供應鏈參與AI運算需求 ，更應該應用AI 來提升整體的生產力，包含R&D研發效率、產業經濟優化與社會應用價值，讓台灣的科技產業更上一層樓，是我們共同需要探索的課題。

聯詠科技-平德林協理 將與各位分享

「IC設計趨勢與機會」

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演講內容簡介：

每個人的生活中都有一隻壓力小怪獸，牠幫助我們往更好的目標前進，但卻也可能壓垮我們的身體與心靈，因此，如何與這隻壓力小怪獸和平共處也就顯得重要。本講座將帶領大家思考自己在目前生活中所扮演的角色，並理解壓力是怎麼在我們的生活中產生，而我們又能如何因應壓力所帶來的影響，以達到生活的平衡。

鴻海研究院量子所-謝明修所長 將與各位分享

「Good Quantum LDPC Codes with Linear Time Decoders」

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演講大綱：

在2023年，記憶體/儲存產業將面臨全新的挑戰，產業將有什麼變化？市場將有什麼挑戰？而群聯電子在其中又有什麼優勢及地位？將由群聯電子創辦人：潘健成執行長向同學分享，同時也將和同學分享自己的經歷以及群聯電子公司多年來的成長和展望。

台灣美光-黃穗麒處長 將與各位分享

「Industry trend, about packaging and experience sharing」

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蠟筆藝術家-王建民老師 將與各位分享

「蠟筆王藝術三部曲」

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演講大綱：

• ESG與企業永續發展
• IC R&D and ESG
• The Power of Green Technology
• Better Life and Future
• Summary

鴻海研究院量子計算研究所-徐銘鍵博士 將與各位分享

「Quantum state tomography via non-convex Riemannian gradient descent」

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台積電 廖思雅處長 將與各位分享

「回顧二十，展望二十，從英特爾到台積電，從美國到台灣」

歡迎有興趣的師長同學一同參加~