Talks
Topic Speaker Date Time Location
AI輔助的圖像處理器和編解碼器 陳彥光博士 2024-07-15 14:00 博理館201
AI輔助的圖像處理器和編解碼器 Speaker:陳彥光博士|IEEE Fellow
When:Date:2024-07-15|TIme:14:00
Where:博理館201
Organizer:電資學院
Co-organizer:電子所
Contact:電資學院
Tel:
Info:

7/15週一下午2:00邀請IEEE Fellow陳彥光博士蒞臨專題演講,主題為:AI輔助的圖像處理器和編解碼器,地點於博理館201會議室,歡迎踴躍出席!!


報名請至:

https://forms.gle/ebD2NN1HbTMzLquu5

Attachment: 無
臺灣草鴞與西拉雅鴞郎的旅程 萬俊明導演 2024-05-27 13:30 博理館113室
臺灣草鴞與西拉雅鴞郎的旅程 Speaker:萬俊明導演|
When:Date:2024-05-27|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

萬俊明導演將與各位分享
「臺灣草鴞與西拉雅鴞郎的旅程」
歡迎有興趣的師長同學一同參加~

Attachment: 無
火災與地震的應變 黃凱馡消防員 2024-05-20 13:30 博理館101室+博理113連線
火災與地震的應變 Speaker:黃凱馡消防員|北市消防局
When:Date:2024-05-20|TIme:13:30
Where:博理館101室+博理113連線
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

北市消防局黃凱馡消防員將與各位分享
「火災與地震的應變」
歡迎有興趣的師長同學一同參加~

Attachment: 無
台大電機到台灣職棒的Trial and Error 施懷勛創辦人 2024-05-13 13:30 博理館113室
台大電機到台灣職棒的Trial and Error Speaker:施懷勛創辦人|有球科技
When:Date:2024-05-13|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

有球科技施懷勛創辦人將與各位分享

「台大電機到台灣職棒的Trial and Error」

歡迎有興趣的師長同學一同參加~

Attachment: 無
先進半導體封裝應用於AI運算之技術趨勢 張欣晴博士 2024-05-06 13:30 博理館113室
先進半導體封裝應用於AI運算之技術趨勢 Speaker: 張欣晴博士|日月光半導體
When:Date:2024-05-06|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:台灣半導體產業協會 (TSIA)
Contact:袁小姐
Tel:
Info:

Abstract:

In recent years, the computing capability of the semiconductor chips is driven not only by the foundry process scaling to the most advanced nodes, but also by the advanced package that heterogeneously integrates chips made by their most competitive process.This growth of computing capability on the one hand enables AI algorithms to deliver their potential, on the other hand expedites novel algorithms to evolve and reach beyond human imagination.

One of the most important trends is to divide and win: using the chiplet approach.The SoC (System on Chip) approach used to put all functions, such as computing units (xPU), memory, logic, I/O, analog, power management etc, into one single chip and its foundry process using its IP.However as system complexity, cost, die size, and design cycle time approach the limits, integration of chiplet from various foundry processes by advanced package become the most cost effective way.In addition, advanced package allows topology of connection, memory integration, power integration into 2.5/3D and vertical, hence implement system that was not possible by single SoC alone.Today, many of the most advanced AI computing solutions are implemented by the chiplet approach, and are making differences in the cloud and edge computing and switching, and in many innovative AI enabled end devices.

Last but not least, power consumption requires for the AI computing becomes critical economically and environmentally for the human civilization as a whole.Advanced package integrates ever-efficient power delivery into the package and optimized at the system level, and allows ultra-low power optical chips be integrated into one single package.

Attachment: 無
認真研究的你,好好休息了嗎? 林子茗專員 2024-04-29 13:30 博理館113室
認真研究的你,好好休息了嗎? Speaker:林子茗專員|台大學輔中心
When:Date:2024-04-29|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

演講內容簡介:

每天花了一整天的時間待在研究室,住處與學校兩點一線,睡前躺在床上還是擔心著自己的研究進度、或是明天meeting可能會面對的狀況,你的生活是這樣嗎?研究生生活並不容易,好好休息,才能走得更為安適與自在。本講座將從研究生可能面對的挑戰與壓力出發,思考可以如何在過程中「好好休息」,維持生活中的平衡並保持前進的動力。

Attachment: 無
AIx 死x 機器人 楊皓宇 執行長 2024-04-22 13:30 博理館113室
AIx 死x 機器人 Speaker:楊皓宇 執行長|Protico (踢可股份有限公司)
When:Date:2024-04-22|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

踢可股份有限公司楊皓宇執行長將與各位分享

「AIx 死x 機器人」

歡迎有興趣的師長同學一同參加~

Attachment: 無
AI世代的EDA- 從元件模擬看EDA工具的挑戰和機會 林忠凱處長 2024-04-15 13:30 博理館113室
AI世代的EDA- 從元件模擬看EDA工具的挑戰和機會 Speaker:林忠凱處長|台積電(技術模擬處TMLD)
When:Date:2024-04-15|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:台大SoC中心
Contact:袁小姐
Tel:
Info:

大綱:

台積公司為500個以上的客戶提供服務,生產超過10000 種不同產品,被廣泛地運用在各種終端市場,例如高效能運算、智慧型手機、物聯網、車用電子與消費性電子產品,不同的客戶產品代表的是不同的製造和設計支援。 過去三十幾年年來,台積公司,供應商,與我們的客戶形成一個大聯盟,不斷的創新,將各種想法付諸實現。講者將從TSMC晶片製造服務的現況出發,藉由元件模擬的角度,討論各種產品衍生的電路設計自動化需求,及其面對的挑戰及發展。也會針對高效能運算設計所需的模擬,探討在人工智慧和機器學習的幫助下,對於傳統電路模擬架構可能的突破。最後,在技術簡介之外,講者也會分享多年的職場經驗,鼓勵大家參與未來無限的可能。

Attachment: 無
穿越憂鬱流沙經驗分享 陳良基教授與王素梅老師 2024-04-01 13:30 博理館101室+博理113連線
穿越憂鬱流沙經驗分享 Speaker:陳良基教授與王素梅老師|
When:Date:2024-04-01|TIme:13:30
Where:博理館101室+博理113連線
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

大綱:

透過陳良基教授與王素梅老師的真實故事,探索憂鬱症的樣貌及其對當事人和家庭的影響。藉由兩位講者分享,了解憂鬱症的挑戰,及如何在支持和被支持的過程中共同成長,一同攜手掙脫流沙的桎梏。

Attachment: 無
AI for wildlife conservation(運用AI技術保育野生動物) 郭晟哲協理 2024-03-25 13:30 博理館113室
AI for wildlife conservation(運用AI技術保育野生動物) Speaker:郭晟哲協理|奇景光電
When:Date:2024-03-25|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:台大SoC中心
Contact:袁小姐
Tel:
Info:

演講大綱:

1. 機器視覺與人工智慧淺談

2. 人工智慧在野生動物的應用與挑戰

3. 奇景光電超低功耗開源人工智慧解決方案

Attachment: 無
混合信號在先進製程的挑戰與ChatGPT帶來的影響 辛東橙處長 2024-03-18 13:30 博理館113室
混合信號在先進製程的挑戰與ChatGPT帶來的影響 Speaker:辛東橙處長|聯詠科技
When:Date:2024-03-18|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:台大SoC中心
Contact:袁小姐
Tel:
Info:

講題大綱:

1.   Mixed-Signal Circuit

2.  全球半導體產品分類與應用佔比

3.  晶片上電路種類與用途

4.  類比電路簡介與有線傳輸介面介紹

5.  先進製程的設計挑戰

6.  ChatGPT的使用與影響

7.  職場經驗分享

Attachment: 無
Lagrangian relaxation based gate sizing for circuit optimization Dr. David Chinnery 2024-03-11 13:30 博理館113室
Lagrangian relaxation based gate sizing for circuit optimization Speaker:Dr. David Chinnery|Architect, Siemens Digital Industries Software
When:Date:2024-03-11|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

Abstract:
Gate sizing in digital circuits is a computationally hard problem. A common heuristic is to greedily resize the gate with the best trade-off for the change in delay vs. the change in area or power, iteratively until it converges, or until a maximum number of iterations. This is relatively fast, but it is quite suboptimal.

The gate-sizing problem can be formulated using Lagrangian relaxation, a machine learning approach, where gates are resized per a local objective with Lagrangian multiplier weighted delay constraints. Then, these multipliers are upsized to reduce constraint violations. It iterates between these two phases until it converges.

This talk will overview some historical circuit gate-sizing techniques, then discuss what is used in commercial electronic design automation software, and the challenges to adopt Lagrangian relaxation based gate-sizing in an industrial design flow. Software techniques to speed it up and reduce memory will also be detailed.

Attachment: 無
閃存猴子的一生 林緯技術長 2024-03-04 13:30 博理館113室
閃存猴子的一生 Speaker:林緯技術長|群聯電子
When:Date:2024-03-04|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:台大SoC中心
Contact:袁小姐
Tel:
Info:

​畢業後一頭栽進快閃記憶體的工程師,他的人生究竟有甚麼閃亮的發展?快閃記憶體究竟是彎道超車的一顆星,還是即將撞上貨車的隕石?此演講將分享閃存猴子在茫茫人生中的深刻體驗。


Attachment: 無
Edge AI Evolution – Opportunity and Challenge 陸忠立協理 2024-02-26 13:30 博理館113室
Edge AI Evolution – Opportunity and Challenge Speaker:陸忠立協理|聯發科技 計算與人工智能技術群 本部
When:Date:2024-02-26|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

Abstract: 

Over the years, edge AI has made significant strides, transitioning from applications like photo classification and face detection to enhancing video and gaming picture quality. The advent of generative AI has further propelled innovation, revolutionizing our life experiences. However, due to intensive computational and memory requirements, current generative AI applications primarily rely on cloud infrastructure.

In this presentation, we aim to explore the emerging trend of shifting from a cloud-centric approach to a collaborative cloud-edge paradigm for generative AI technologies. We will delve into the multitude of opportunities and challenges that lie ahead when supporting generative AI on edge devices. This transformation entails a synergetic blend of technological advancements, enhancements in hardware architecture, and the reduction of computational complexities, ultimately enabling the realization of novel generative AI applications.

Attachment: 無
Future Systems-on-Chip for Full Spectrum Utilization from RF to Optics 張懋中特聘研究講座 2024-02-19 13:55 博理館101室+博理113連線
Future Systems-on-Chip for Full Spectrum Utilization from RF to Optics Speaker:張懋中特聘研究講座|台大電子所
When:Date:2024-02-19|TIme:13:55
Where:博理館101室+博理113連線
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

臺大電子所特聘研究講座-張懋中博士將與各位分享

「Future Systems-on-Chip for Full Spectrum Utilization from RF to Optics」

歡迎有興趣的師長同學一同參加~

Attachment: 無
半導體產業面面觀 楊光磊博士 2023-12-11 13:30 博理館101室
半導體產業面面觀 Speaker:楊光磊博士|前台積電研發處長
When:Date:2023-12-11|TIme:13:30
Where:博理館101室
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

前台積電研發處長-楊光磊博士將與各位分享

「半導體產業面面觀」

歡迎有興趣的師長同學一同參加~


Attachment: 無
Wireless AI: A New Sixth Sense to Deciphering our World 劉國瑞博士 2023-12-04 13:30 博理館101室+博理113連線
Wireless AI: A New Sixth Sense to Deciphering our World Speaker:劉國瑞博士|2022 年 IEEE 全球總裁與首席執行長
When:Date:2023-12-04|TIme:13:30
Where:博理館101室+博理113連線
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:
Attachment: 無
Memory Packaging Technology Roadmap Jackson Huang 黃耀德處長 2023-11-27 13:30 博理館113室
Memory Packaging Technology Roadmap Speaker:Jackson Huang 黃耀德處長|台灣美光
When:Date:2023-11-27|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:台大SoC中心
Contact:袁小姐
Tel:
Info:

演講大綱/摘要:

1. Introduction to Package
2. Micron Packaging Sites
3. Package Trend


Attachment: 無
每個人都是一本小說 周景揚校長 2023-11-20 13:30 博理館101室+博理113連線
每個人都是一本小說 Speaker:周景揚校長|國立中央大學
When:Date:2023-11-20|TIme:13:30
Where:博理館101室+博理113連線
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

國立中央大學 周景揚校長將與各位分享

「每個人都是一本小說」

歡迎有興趣的師長同學一同參加~


Attachment: 無
Applications of Edge Intelligence Vision Device 王裕閔副處長 2023-11-13 13:30 博理館113室
Applications of Edge Intelligence Vision Device Speaker: 王裕閔副處長|聯詠科技iVoT產品事業處
When:Date:2023-11-13|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:台大SoC中心
Contact:袁小姐
Tel:
Info:

聯詠科技iVoT產品事業處 王裕閔 副處長將與各位分享

Applications of Edge Intelligence Vision Device

歡迎有興趣的師長同學一同參加~

Attachment: 無
人生風景無限 一條路 走就對了 麥覺明導演 2023-11-06 13:30 博理館113室
人生風景無限 一條路 走就對了 Speaker:麥覺明導演|大麥影像傳播工作室
When:Date:2023-11-06|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

大麥影像傳播工作室 麥覺明導演將與各位分享

「人生風景無限 一條路 走就對了」

歡迎有興趣的師長同學一同參加~

Attachment: 無
談新鮮人如何建構未來競爭力 林佳璋總經理 2023-10-30 13:30 博理館113室
談新鮮人如何建構未來競爭力 Speaker:林佳璋總經理|展碁國際
When:Date:2023-10-30|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

展碁國際 林佳璋總經理將與各位分享

「談新鮮人如何建構未來競爭力」

歡迎有興趣的師長同學一同參加~

Attachment: 無
Quantified Benchmarking: A Key Role of Electronic Design Automation for Heterogenous Integration Manufacturing Prof. Sung Kyu Lim 2023-10-23 15:30 BL113
Quantified Benchmarking: A Key Role of Electronic Design Automation for Heterogenous Integration Manufacturing Speaker:Prof. Sung Kyu Lim|Georgia Institute of Technology
When:Date:2023-10-23|TIme:15:30
Where:BL113
Organizer:電子所
Co-organizer:SOC中心
Contact:陳中平
Tel:
Info:

Heterogeneous integration poses new challenges to electronic design automation (EDA) and packaging communities and demands innovative solutions that must be built together with tight-knit collaborations. One key outcome is the EDA-enabled benchmarking capability that provides quantified evaluation of manufacturing technologies under development using system-level design metrics of interest. We present two such examples, first on glass vs. silicon as the interposer material choices, and second on hybrid bonding vs. micro bumping as the die bonding options, both targeting system-level power, performance, area, and cost (PPAC) optimization. In addition, thermal, power delivery, and other reliability related metrics are calculated and compared. Lastly, we discuss various algorithms and methodologies developed to enable these EDA tools that are based on conventional and AI approaches.

Attachment: 無
Logic Synthesis for BeyondCMOS Technologies Siang-Yun Lee 2023-10-19 10:30 BL201
Logic Synthesis for BeyondCMOS Technologies Speaker:Siang-Yun Lee|EPFL
When:Date:2023-10-19|TIme:10:30
Where:BL201
Organizer:電子所
Co-organizer:SOC中心
Contact:陳中平
Tel:
Info:

Logic synthesis, as an essential step in the VLSI design automation flow, has been developed with the characteristics of CMOS digital circuits in mind. However, with the increasing demand for computationally-heavy applications, researchers have been investigating various beyond-CMOS technologies featuring faster computation speed and/or lower energy consumption. These emerging technologies often have distinct characteristics and constraints to be taken into account in logic synthesis. For example, some technologies are based on majority gates, instead of NAND gates; some technologies have pathbalancing and fanout constraints; and some technologies require a planar circuit layout, where wire crossings also need to be balanced. In this talk, I will discuss how modern logic synthesis techniques may be applied to, or adapted for, beyond-CMOS technologies with special characteristics.

Attachment: 無
從IDF數控飛操系統開發經驗談技術轉移的陷阱 杲中興前院長 2023-10-16 13:30 博理館101室
從IDF數控飛操系統開發經驗談技術轉移的陷阱 Speaker:杲中興前院長|中科院
When:Date:2023-10-16|TIme:13:30
Where:博理館101室
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

中科院前院長 杲中興院長將與各位分享

「從IDF數控飛操系統開發經驗談技術轉移的陷阱」

歡迎有興趣的師長同學一同參加~

Attachment: 無
車載顯示IC技術發展 徐正池資深處長 2023-10-02 13:30 博理館113室
車載顯示IC技術發展 Speaker:徐正池資深處長|奇景光電
When:Date:2023-10-02|TIme:13:30
Where:博理館113室
Organizer:電子所
Co-organizer:台大SoC中心
Contact:袁小姐
Tel:
Info:

奇景光電-徐正池資深處長 將與各位分享

「車載顯示IC技術發展」

歡迎有興趣的師長同學一同參加~

Attachment: 無
Recent Progresses of Compute-in-Memory Prototype Chips: RRAM, 3D integration and Ferroelectric Technologies Prof. Shimeng Yu 2023-09-27 13:30 電機二館105室
Recent Progresses of Compute-in-Memory Prototype Chips: RRAM, 3D integration and Ferroelectric Technologies Speaker:Prof. Shimeng Yu|Georgia Institute of Technology
When:Date:2023-09-27|TIme:13:30
Where:電機二館105室
Organizer:臺大電子工程學研究所
Co-organizer:臺大SOC中心 / 聯發科-臺大創新研究中心 / 臺大重點科技研究學院
Contact:邱玉霜
Tel:33663718
Info:

Speaker: Prof. Shimeng Yu (Georgia Institute of Technology)

Topic: Recent Progresses of Compute-in-Memory Prototype Chips: RRAM, 3D integration and Ferroelectric Technologies

Abstract:

In this presentation, we will present the recent progresses on the compute-in-memory (CIM) prototype chips. Mixed-signal resistive random access memory (RRAM) based CIM can process the multiply-accumulate (MAC) functions in deep neural networks efficiently, thus it is regarded as a competitive solution for AI hardware design for edge intelligence. We recently taped out two generations of RRAM CIM macros in TSMC  40 nm process. The following features are supported in these macros: 1) Adaptive input sparsity control; 2) Reconfigurable weight precision; 3) Integrated digital compute units; 4) Input-aware on-chip ADC reference; 5) On-chip write-verify controller; 6) Input encoding for embedded security; 7) ADC-less communication between sub-arrays with pulse-width-modulation; 8) In-situ error correction code that preserves the MAC parallelism.  We will introduce these design techniques and silicon measurement results. Next the prospects and challenges of CIM chip design will be discussed. Leveraging the advanced packaging techniques, 3D physical design partition and 3D processing-element (PE) cube design is proposed to scale the RRAM CIM macro with digital PE for larger neural network (e.g., vision transformer). Assembly of many 3D PE cubes in a 2.5D integrated silicon interposer could potentially extend the support for large language model (e.g., GPT). Finally, switching the technology from RRAM to ferroelectric devices could further improve the energy efficiency due to the reduced static power via charge-domain computing.

Bio:

Shimeng Yu is a full professor of electrical and computer engineering at Georgia Institute of Technology. He received the Ph.D. degree in electrical engineering from Stanford University in 2013. From 2013 to 2018, he was an assistant professor at Arizona State University. Prof. Yu’s research expertise is on the emerging non-volatile memories for applications such as deep learning accelerator, in-memory computing, and 3D integration.  Prof. Yu currently serves technical program committee for the IEEE Symposium on VLSI Technology and Circuits, and also serves an editor for IEEE Electron Device Letters (EDL). He is a senior member of the IEEE.

報名連結: https://forms.gle/PS5ZuQrwAYp5JNKN8

主辦單位臺大電子所

協辦單位臺灣大學重點科技研究學院 / 聯發科技-臺大創新研究中心/ 臺大SOC中心

演講聯絡人:

臺大電子所專任助理

邱玉霜 Susan Chiou

yuhshuang@ntu.edu.tw

02-33663718

台北市羅斯福路四段一號電機二館308室

Attachment: 無
研究生不可不知的文獻搜尋方法 洪翠錨編審 2023-09-25 13:30 博理館101室
研究生不可不知的文獻搜尋方法 Speaker:洪翠錨編審|臺大圖書館學科服務組
When:Date:2023-09-25|TIme:13:30
Where:博理館101室
Organizer:電子所
Co-organizer:臺大圖書館
Contact:袁小姐
Tel:
Info:

演講大綱/摘要:

介紹臺大圖書館豐富館藏資源與服務,並說明參考文獻類型與查詢途徑及技巧、引用文獻資料庫(Web of Science與Scopus)與IEEE Xplore、引文格式與書目管理軟體、Open Access 與獲取文獻全文方法等,有助於提升研究生的資訊素養,讓課業學習與論文寫作更加順遂。

Attachment: 無
A Low-Power 28-GHz Beamforming Receiver with On-Chip LO Synthesis Prof. Behzad Razavi 2023-09-22 16:30 電機二館142會議室
A Low-Power 28-GHz Beamforming Receiver with On-Chip LO Synthesis Speaker:Prof. Behzad Razavi|University of California, Los Angeles
When:Date:2023-09-22|TIme:16:30
Where:電機二館142會議室
Organizer:重點科技研究學院、IEEE SSCS Taipei Chapter
Co-organizer:國科會關鍵新興晶片設計研發計畫辦公室
Contact:顏小姐
Tel:
Info:


本次活動有興趣可至連結報名:https://forms.gle/55RzzDH5gAN36JBV9

演講大綱﹕

The use of millimeter-wave communications in 5G radios becomes viable if extensive beamforming is employed to overcome the high path loss and the power consumption is sufficiently low to afford frequent high-throughput connections for mobile devices. Recent beamforming receivers in the vicinity of 28 GHz draw, per element, 28 mW to 50 mW. Moreover, most reported receivers do not include complete on-chip LO synthesis.

A key observation in the design of beamforming receivers is that the phase shift network typically consumes high power whether it appears in the RF path or the LO path. This presentation introduces a new technique that avoids the bandwidth-loss-phase shift tradeoffs of conventional topologies. In addition, several other new concepts are offered that reduce the power with no noise figure penalty. Fabricated in TSMC’s 28-nm CMOS technology, the eight-element prototype draws 166 mW, achieving a minimum noise figure of 3.7 dB, a phase resolution of 11.7 degrees,and an LO jitter of 155 fs.

作者簡介

Behzad Razavi is Professor of Electrical Engineering at UCLA, where he conducts research on analog and RF integrated circuits. Prof. Razavi has served as an IEEE Distinguished Lecturer and published more than 200 papers and eight books. He has received nine IEEE best paper awards and six teaching and education awards, and his books have been published in seven languages. He received the IEEE Pederson Award in Solid-State Circuits and was recognized as one of the top ten authors in the 50-year history of the IEEE International Solid-State Circuits Conference. He is a member of the US National Academy of Engineering and a fellow of the US National Academy of Inventors.

Attachment: 無
Business Sense for Engineers 項春申創辦人 2023-09-18 13:30 博理館101室
Business Sense for Engineers Speaker:項春申創辦人|瓦雷科技
When:Date:2023-09-18|TIme:13:30
Where:博理館101室
Organizer:電子所
Co-organizer:
Contact:袁小姐
Tel:
Info:

瓦雷科技-項春申創辦人 將與各位分享

「Business Sense for Engineers」

歡迎有興趣的師長同學一同參加~

Attachment: 無