Our research focuses cover all aspects of VLSI physical design (PD) (partitioning, floorplanning, placement, routing, and post-layout optimization), electrical effects and design for manufacturing for nanometer ICs, and design automation for biochips. Currently, we are executing 9 research projects, including 6 from industry (physical design for nanometer ICs, large-scale circuit placement, Multiple supply voltage design for power integrity optimization, multilevel gridless routing, and PD for flip-chip and layout co-design), and 4 from NSC (gridless routing, design for manufacturing, PD for trillion-scale circuit systems, and routing tree synthesis). Our lab has a collection of 400+ books for research in electronic design automation, one of the most complete collections in this area. The lab is equipped with 30+ CPUs of workstations and PC servers. Each member is also equipped with at least one laptop and one desktop computer for research. The lab has been publishing the most papers at DAC and ICCAD every year since 2007. Yao-Wen Chang * 2020/2021 President, IEEE Council on EDA (CEDA) * 2012/2019 Secretary/VP/President-elect, IEEE CEDA * 2013/2014 ICCAD Technical Program Chair / General Chair * 2010/2011/2012 ISPD Technical Program Chair / General Chair / Steering Committee Chair * 2017 DAC Best Paper Award (10 Best Paper Awards, 5 DAC & 5 ICCAD BPA Nominations) * 2013 Four DAC Research Awards (1st Most Papers in the 5th Decade, etc.) * 64 papers in DAC (#2 worldwide), 66 papers in ICCAD (#3 worldwide), 70 papers in TCAD (#4) * Six 1st-place & 21 top-3 awards of SigDA/CEDA EDA Contests

VLSI SoC&EDA lab is an international lab with a research emphysis on the VLSI-CAD and Microprocessor design. In the VLSI CAD part, we are focusing on the physical design, timing analysis, circuit simulation and optimization, and the cure for process variation. Recently, we are working on developing the optical lithography simulation and OPC.

The main research emphasis of ALCom Lab is on applying logic and computation methods for the analysis and construction of electronic systems. There are three main directions include "logic synthesis and verification," "optimization and decision procedures," and "computation models." For logic synthesis and verification, we are concerned with logic circuit optimization and verification, logic data structure manipulation and application, temporal and logic constraint solving, etc. For optimization and decision procedure, we work on satisfiability (SAT), stochastic Boolean satisfiability (SSAT), quantified Boolean formula (QBF), dependency quantified Boolean formula (DQBF), mathematical programming and explore their applications. For computation models, we study computation and circuit design with quantum physics, biochemical reactions, and neural networks. We explore important cutting-edge problems and devise new methods to solve them. We are under active international and industrial cooperation.

Our lab is located at BL-427 please visit websites http://cc.ee.ntu.edu.tw/~cmli http://lads.ee.ntu.edu.tw

The goal of the DfT research team is to develop hardware testing and security solutions. The main research topics include: (1) software-based self-testing for processor cores, (2) design-for-test techniques for heterogeneous integration, and (3) hardware security and trust.

Lab of Dependable Systems (3) Design Verification Team The research focus of our lab is in the SoC (System on a Chip) design verification area, which includes: 1. Sequential verification engines (e.g. ATPG, SAT, BDD, Arithmetic solver, etc), 2. Network, communication, and multimedia IP verification techniques, 3. Design for Verifiability (DfV), 4. System design analysis and debugging techniques, 5. Various applications of Constraint Satisfaction Problem (CSP). We are implementing the above research topics into our own tools: 1. Property Verification Framework, 2. IP Qualification Framework.

IRIS lab provides a cozy place to train critical and creative thinking. Every student obtains guidance directly from the coach. We co-work to solve interesting, practical, and timely problems. The research interests lie primarily in the area of Electronic Design Automation, particularly in 1) timing analysis and optimization, 2) engineering change order optimization, 3) physical design automation, 4) design for manufacturability, 5) data analytics based design automation. We have been working closely with the semiconductor industry.

Nanoscale Design and Fabrication Systems Laboratory Located at R604 and R255 of the Min-Da and EEII buildings respectively, NDFSL is supervised by Prof. Kuen-Yu Tsai. The main research theme is the application of advanced control, signal processing, and optimization techniques to nanolithography and nanotechnology related problems, especially for the design and fabrication of nanometer VLSI circuits. Current research topics include: (1) Nanolithography processes and equipment: Next generation lithography (NGL) based on multiple-electron-beam-direct-write (MEBDW) and extreme ultraviolet (EUV) light. (2) Nanolithography software: Lithography simulation, resolution enhancement techniques (RET), and design for manufacturability (DFM). (3) Nanolithography process and equipment control: Advanced process control (APC), advanced equipment control (AEC), and fault detection/classification (FDC); High-accuracy alignment and overlay algorithms. (4) Circuit design automation by control and optimization techniques: Design of actuation/sensor/power circuits; Automatic circuit/layout generation and optimization. (5) Sensor/actuator array systems and signal processing: Electron-beam position monitor system based on MEMS and sensor fusion technologies. Mixed-signal circuit design for laser interferometers.