1.探討工程師除了寫程式之外，如何透過提升領導與溝通技能來擴大影響力。

2.分享從初階 (E3) 到資深 (E4/E5) 工程師的成長歷程，以及在不同階段公司（如 Facebook、Cooby、PicCollage）的觀察。

3.人生導航指引：分享「學習極大化 (Maximize Learnings)」與「目標導向 (Goal Oriented)」的人生哲學。​

每天花了一整天的時間待在研究室，住處與學校兩點一線，睡前躺在床上還是擔心著自己的研究進度、或是明天meeting可能會面對的狀況，你的生活是這樣嗎？研究生生活並不容易，好好休息，才能走得更為安適與自在。本講座將從研究生可能面對的挑戰與壓力出發，思考可以如何在過程中「好好休息」，維持生活中的平衡並保持前進的動力。

Title:
Advancing ML for EDA: From Secure Data to Generative AI

Speaker:

Dr. Chen-Chia Chen, NVIDIA

Time:

15:00-16:00, December 23 (Tuesday)

Place:

Room 145, EE2 Building, National Taiwan University

Abstract:
The rise of machine learning (ML) technology inspires a boom in its applications in electronic design automation (EDA) and helps improve the degree of automation in chip designs. However, we observe some obstacles in the traditional ML for EDA (ML4EDA) model development flow that would prolong and hinder the model development, including data availability, model architecture design, and model commercialization. Parallel to developments in ML4EDA, generative AI, especially large language models (LLMs), has opened new frontiers in numerous fields by demonstrating capabilities in generating complex structures. Thus, in this talk, I will introduce an advanced ML4EDA model development flow and generative AI techniques for DRC code generation and analog topology design.

Bio:
Chen-Chia is currently an ML engineer at NVIDIA, working on analog layout automation. He completed his Ph.D. in Electrical and Computer Engineering at Duke University, under the advisement of Prof. Yiran Chen in the CEI Lab. He received his B.S. in Electrical Engineering from National Taiwan University in 2020. His research focuses on novel EDA methods, especially for machine learning and generative AI methodologies. He won the best paper award and best paper candidate at ASPDAC’25. He also received second place at the ISPD’19 Detailed Routing Contest and Honorable Mention at ICCAD’20 CAD Contest. 

講師簡介

專長登山、越野跑等戶外運動，職業戶外賽事策劃人，曾參與國內外大型戶
外運動賽事，知名的包含戈壁挑戰賽、TNF100、紅牛24 小時，及國際級戶外
挑戰賽等。曾獲選深圳十佳戶外教練及特殊貢獻獎。
近年在推廣高齡體適能運動，透過運動和飲食等衛教達到健康促進的效益。
目前為台大癌醫中心、台大EMBA 門外社、永福扶輪社及多家企業特聘的體適
能教練。也與台大森林系、台灣森林保健學會和林務局等單位合作，培訓森
林療癒引導員，打造『綠色健身房』，推進全民健康的發展。
現任：
跑山幫越野跑團創辦人
台大田徑校友會理事
深圳青少年成長計劃顧問
深圳山地救援隊教練
領攀山地戶外運動學校講師
林務局森林療癒師培訓講師
台灣森林保健學會講師
台大森林系森林療癒課程客座講師
輔大企管系業師
曾任相關職務：
深圳青少年成長計劃創始人、導師
深圳登協培訓部副部長
深圳登協高山探險部部長
戶外運動相關經歷：
深圳登協戶外教練、凱樂石簽約運動員/教練、The North Face 簽約教練
內蒙、新疆、山東、雲南等地戶外教練班教練
雲南省登協戶外裁判班主教練

講題：
掌握學術研究的黃金法則：圖書館資源與AI素養

演講簡介：
這場講座將帶您掌握學術研究的黃金法則：精準運用圖書館資源，從文獻檢索、全文取得、投稿選刊，到學術倫理與AI素養，全方位提升您的研究效率與品質，讓您在學術道路上事半功倍。

講綱：

1.精準鎖定主題： 學習檢索詞策略，找到你的研究方向。
2.高效文獻檢索： 運用圖書館資料庫，快速篩選核心文獻。
3.無縫全文獲取： 認識多種管道，輕鬆讀取完整內容。
4.投稿選刊策略： 掌握期刊評估技巧，為你的論文找到最佳歸宿。
5.善用AI助手： 培養正確的AI素養，提升研究效率與品質。
6.專業諮詢服務： 了解圖書館如何成為你的學術後盾。

講題：Semiconductor Everywhere: Explore IC Design at TSMC

Semiconductors play a pivotal role in our modern digital world. Far more than mere electronic components, they are the very lifeblood of our digital existence, powering every innovation and connecting our world. At the heart of this advancement, TSMC boasts a complete and robust design team - a collective of brilliant minds meticulously crafting and optimizing every chip. The exceptional work of this team forms the cornerstone ensuring the efficient operation of all modern technological products, from smartphones to AI servers. We will briefly illustrate the complex process of IC design and how TSMC's team, through rigorous design and optimization, transforms cutting-edge technological concepts into tangible chip products.

講員：台積電 徐孟楷資深經理(DTP前瞻設計方案與技術標竿處 )

Meng-Kai Hsu received his B.S. degrees in electronics engineering and computer science from National Chiao Tung University (NCTU), Hsinchu, Taiwan, in 2007, and his Ph.D. degree from the Graduate Institute of Electronics Engineering, National Taiwan University (NTU), Taipei, Taiwan, in 2012. Dr. Hsu is currently a Department Manager in the Design Flow Development Department within the Design and Technology Platform (DTP) at Taiwan Semiconductor Manufacturing Company, Ltd. (TSMC). He is responsible for advanced technology assessment, physical design enablement, and AI/ML design methodology development. Dr. Hsu holds over 20 U.S. patents and received the Excellent Young Engineer Award from the Chinese Institute of Engineers in 2025.

[演講訊息]

Analog Design Experiments with AI

演講者：Prof. Behzad Razavi(University of California, Los Angeles )

時間：2025年09月24(三)下午4:00~5:00

地點：國立台灣大學電機二館105演講廳

本次活動有興趣可至連結報名：https://reurl.cc/E6V8KR

演講大綱﹕

With the rapid rise of AI in various fields, we naturally wonder whether it can help or even replace analog designers. As a first step in our investigation, we evaluate the present capabilities of ChatGPT and probe its conceptual understanding beyond what it can find online. We limit our study to undergraduate analog CMOS circuits, pose questions to ChatGPT, and analyze the answers that it provides. We report answers of which many are surprising, either because they are not obvious but correct or because they are obvious but incorrect. Whether or not AI  will replace analog designers in the near future will be clear by the end of the presentation.

作者簡介﹕

Behzad Razavi is Professor of Electrical Engineering at UCLA, where he conducts research on analog and RF integrated circuits. Prof. Razavi has served as an IEEE Distinguished Lecturer and published more than 200 papers and nine books. He has received nine IEEE best paper awards and six teaching and education awards, and his books have been published in seven languages. He received the IEEE Pederson Award in Solid-State Circuits and was recognized as a top author in the 50-year and 75-year histories of the IEEE International Solid-State Circuits Conference. He is a member of the US National Academy of Engineering and a fellow of the US National Academy of Inventors.

https://forms.gle/BUbCCdqsCdfbcFW46

Abstract:

Power Consumption is more and more a major issue in the design of integrated systems and circuits. The optimization of the In designs must be done in all level of design abstraction, this means in all steps of the design flow. But, we will focus on optimization at logic and physical design level. Nowadays, most circuits use much more transistors than needed. A way to reduce power consumption at physical level is to reduce the number of transistors used to implement a circuit, as leakage power is proportional to the number of transistors. It is shown a physical design approach to reduce the number of transistors needed to perform a task.  It is proposed an EDA tool set to automatically generate the physical design of any transistor network. It shows an important reduction on power, improving also reliability. A standard cell library has a limited number of logical functions, and a limited number of sizings. The lecture is target in optimization methods to reduce the number of transistors of a circuit. The methods allow the  automatic generation of any possible logical function or transistor network, and using any transistor sizing. It is included comparisons with solutions using the traditional standard cell methodology.

Bio: 

Ricardo Reis received a Bachelor degree in Electrical Engineering from Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, Brazil, in 1978, and a Ph.D. degree in Microelectronics from the National Polytechnic Institute of Grenoble (INPG), France, in 1983. Doctor Honoris Causa by the University of Montpellier in 2016. He is a full professor at the Informatics Institute of Federal University of Rio Grande do Sul. His main research includes physical design automation, design methodologies, fault tolerant systems and microelectronics education. He has more than 700 publications including books, journals and conference proceedings. He was vice-president of IFIP (International Federation for Information Processing) and he was also president of the Brazilian Computer Society (two terms) and vice-president of the Brazilian Microelectronics Society. He is an active member of CASS and he received the 2015 IEEE CASS Meritorious Service Award. He was vice-president of CASS for two terms (2008/2011). He is the founder of the Rio Grande do Sul CAS Chapter, which got the World CASS Chapter of The Year Award 2011, 2012, 2018 and 2022, and R9 Chapter of The Year 2013, 2014, 2016, 2017 and 2020. He is a founder of several conferences like SBCCI and LASCAS, the CASS Flagship Conference in Region 9. He was the General or Program Chair of several conferences like IEEE ISVLSI, SBCCI, IFIP VLSI-SoC, ICECS, PATMOS. Ricardo was the Chair of the IFIP/IEEE VLSI-SoC Steering Committee, vice-chair of the IFIP WG10.5 and he is Chair of IFIP TC10. He also started with the EMicro, an annually microelectronics school in South Brazil. In 2002 he received the Researcher of the Year Award in the state of Rio Grande do Sul. He is a founding member of the SBC (Brazilian Computer Society) and also founding member of SBMicro (Brazilian Microelectronics Society). He was member of CASS DLP Program (2014/2015), and he has done more than 70 invited talks in conferences. Member of IEEE CASS BoG and IEEE CEDA BoG. He is the CASS representative at the IEEE IoT TC. Ricardo received the IFIP Fellow Award in 2021 and the ACM/ISPD Lifetime Achievement Award in 2022. He received the 2023 IEEE CASS John Choma Educational Award.

Registration form: https://forms.gle/Gy8RXYAyQkmYb2Ak9