|Dependable Distributed Systemand Networks Laboratory||Kuo, Sy-Yen||
Professor Sy-Yen Kuo is heading the Dependable Distributed System and Networks Laboratory in the Department of Electrical Engineering at NTU, which focuses on the research of dependable netowrks and systems, SoC design verification, and quantum computing and communication. Nowadays, more and more complicated development of hardware/software systems and wired/wireless networks has made fault tolerance a very important issue in designing information systems to provide services with high dependability and high availability. Among his current research interests are mobile computing and networks, dependable distributed systems, and quantum computing. Prof. Kuo has involved in many important research projects, such as Elastic and Dependable Internet-of-Thing Cloud Service Platform and Its Application in Productivity 4.0, Energy-efficient Data Management based on Software Defined Approach for Multi-tenant IoT Services in Datacenters sponsored by MOST, and Network Anomaly Detection Based on Machine Learning Approach sponsored by Institute for Information Industry.
|The Electronic Design Automation (EDA) Laboratory||Chang, Yao-Wen||
Our research focuses cover all aspects of VLSI physical design (PD) (partitioning, floorplanning, placement, routing, and post-layout optimization), electrical effects and design for manufacturing for nanometer ICs, and design automation for biochips. Currently, we are executing 9 research projects, including 6 from industry (physical design for nanometer ICs, large-scale circuit placement, Multiple supply voltage design for power integrity optimization, multilevel gridless routing, and PD for flip-chip and layout co-design), and 4 from NSC (gridless routing, design for manufacturing, PD for trillion-scale circuit systems, and routing tree synthesis). Our lab has a collection of 400+ books for research in electronic design automation, one of the most complete collections in this area. The lab is equipped with 30+ CPUs of workstations and PC servers. Each member is also equipped with at least one laptop and one desktop computer for research. The lab has been publishing the most papers at DAC and ICCAD every year since 2007. Yao-Wen Chang * 2020/2021 President, IEEE Council on EDA (CEDA) * 2012/2019 Secretary/VP/President-elect, IEEE CEDA * 2013/2014 ICCAD Technical Program Chair / General Chair * 2010/2011/2012 ISPD Technical Program Chair / General Chair / Steering Committee Chair * 2017 DAC Best Paper Award (10 Best Paper Awards, 5 DAC & 5 ICCAD BPA Nominations) * 2013 Four DAC Research Awards (1st Most Papers in the 5th Decade, etc.) * 64 papers in DAC (#2 worldwide), 66 papers in ICCAD (#3 worldwide), 70 papers in TCAD (#4) * Six 1st-place & 21 top-3 awards of SigDA/CEDA EDA Contests
|VLSI SOC&EDA Lab||Chen, Chung-Ping||
VLSI SoC&EDA lab is an international lab with a research emphysis on the VLSI-CAD and Microprocessor design. In the VLSI CAD part, we are focusing on the physical design, timing analysis, circuit simulation and optimization, and the cure for process variation. Recently, we are working on developing the optical lithography simulation and OPC.
|ALCom Lab: Laboratory for Applied Logic & Computation in System Design||Jiang, Jie-Hong||
The main research emphasis of ALCom Lab is on applying logic and computation methods for the analysis and construction of electronic systems. There are three main directions include "logic synthesis and verification," "optimization and decision procedures," and "computation models." For logic synthesis and verification, we are concerned with logic circuit optimization and verification, logic data structure manipulation and application, temporal and logic constraint solving, etc. For optimization and decision procedure, we work on satisfiability (SAT), stochastic Boolean satisfiability (SSAT), quantified Boolean formula (QBF), dependency quantified Boolean formula (DQBF), mathematical programming and explore their applications. For computation models, we study computation and circuit design with quantum physics, biochemical reactions, and neural networks. We explore important cutting-edge problems and devise new methods to solve them. We are under active international and industrial cooperation.
|Lab of Dependable Systems (LaDS)||Li, Chien-Mo||
Our research focuses on VLSI testing and diagnosis techniques, especially for digital circuits. The major topics are: (1) Automatic Test Pattern Generation, ATPG (2) VLSI Diagnosis and Yield Improvement (3) Low Power Testing and IR drop analysis (4) Asynchronous Circuit DfT and BIST (5) Machine Learning for test data analysis for more details, http://cc.ee.ntu.edu.tw/~cmli http://lads.ee.ntu.edu.tw
|Lab of Dependable Systems (LaDS)||Huang, Jiun-Lang||
The goal of the DfT research team is to develop hardware test and security solutions. The main research topics include: (1) software-based on-line self-testing, (2) FPGA-based automatic test equipment, and (3) hardware and blockchain based security and trust.
|Lab of Dependable Systems (LaDS)||Huang, Chung-Yang||
Lab of Dependable Systems (3) Design Verification Team The research focus of our lab is in the SoC (System on a Chip) design verification area, which includes: 1. Sequential verification engines (e.g. ATPG, SAT, BDD, Arithmetic solver, etc), 2. Network, communication, and multimedia IP verification techniques, 3. Design for Verifiability (DfV), 4. System design analysis and debugging techniques, 5. Various applications of Constraint Satisfaction Problem (CSP). We are implementing the above research topics into our own tools: 1. Property Verification Framework, 2. IP Qualification Framework.
|IRIS Lab||Jiang, Hui-Ru||
IRIS lab provides a cozy place to train critical and creative thinking. Every student obtains guidance directly from the coach. We co-work to solve interesting, practical, and timely problems. The research interests lie primarily in the area of Electronic Design Automation, particularly in 1) timing analysis and optimization, 2) engineering change order optimization, 3) physical design automation, 4) design for manufacturability, 5) data analytics based design automation. We have been working closely with the semiconductor industry.
|Nanoscale Design and Fabrication Systems Lab.||Tsai, Kuen-Yu||
Nanoscale Design and Fabrication Systems Laboratory Located at R604 and R255 of the Min-Da and EEII buildings respectively, NDFSL is supervised by Prof. Kuen-Yu Tsai. The main research theme is the application of advanced control, signal processing, and optimization techniques to nanolithography and nanotechnology related problems, especially for the design and fabrication of nanometer VLSI circuits. Current research topics include: (1) Nanolithography processes and equipment: Next generation lithography (NGL) based on multiple-electron-beam-direct-write (MEBDW) and extreme ultraviolet (EUV) light. (2) Nanolithography software: Lithography simulation, resolution enhancement techniques (RET), and design for manufacturability (DFM). (3) Nanolithography process and equipment control: Advanced process control (APC), advanced equipment control (AEC), and fault detection/classification (FDC); High-accuracy alignment and overlay algorithms. (4) Circuit design automation by control and optimization techniques: Design of actuation/sensor/power circuits; Automatic circuit/layout generation and optimization. (5) Sensor/actuator array systems and signal processing: Electron-beam position monitor system based on MEMS and sensor fusion technologies. Mixed-signal circuit design for laser interferometers.
|Fast Crypto Lab||Cheng, Chen-Mou||
Lead by Professor Chen-Mou Cheng, Fast Crypto Lab (FCL) is located in room 631 of the new MD building. FCL’s main research area is cryptographic hardware and embedded systems (CHES), as well as electronic system-level (ESL) design. Currently, FCL’s main research activities focus on the design and analysis of efficient algorithms to solve several important problems arising from cryptology, as well as the development and implementation of these algorithms on massively parallel computers. These problems include solving systems of polynomial equations over finite fields, integer factorization, elliptic-curve discrete logarithm, and lattice reduction. Massively parallel computers like graphics processing units (GPUs) and field-programmable gate arrays (FPGAs) are a new paradigm of high-performance computing. Currently, programming such systems relies on the use of general-purpose programming languages such as CUDA and OpenCL, or general-purpose hardware description languages such as Verilog and VHDL. These general-purpose programming tools are not suitable for developing cryptographic or cryptanalytic systems, not only because these systems are usually highly complicated, but also because the security of a system depends on that of the weakest link, and hence if there are any mistakes in the development process of any components, the security of the entire system could be at stake. Because of this, at FCL we are developing system-level design tools that are more suitable for developing cryptographic and information-security applications. These tools include new programming languages and optimizing compilers that make development easier and less error-prone. On the other hand, we also seek the possibility of applying some cryptographic and cryptanalytic algorithms to solve similar problems in electronic design automation (EDA), e.g., using fast system solvers to help optimize resource allocation and scheduling in a variety of electronic systems. Besides the preceding fundamental research, we are also actively engaged in applied, more practical information-security research that plays a very important role in our daily life. This includes the design and implementation of secure components for electronic payment systems, security analysis of radio-frequency identification (RFID) systems (such as the EasyCard used in Taipei Metro Rapid Transit System), botnet detection and mitigation, and cloud computing security. For further information of Fast Crypto Lab, please visit us on Facebook (http://www.facebook.com/group.php?gid=130560250287403).
|Device and Circuit Lab||Kuo, James-B.||
Our lab is led by Dr. James B. Kuo. We focus on CMOS device modeling and circuit design techniques, including low-voltage CMOS VLSI circuits and SPICE compact modeling of bulk and SOI CMOS devices.
|CAD System Lab||Chen, Sao-Jie||
CAD System Lab is located in Room 407 of BL Building and administered by Prof. Sao-Jie Chen. The research interests of our Lab include: Physical Design in SoC, SoC Hardware/Software Codesign, and Analog IC Design. Physical Design researches are focused on the design automation of floorplanning and routing, which include derivation of new algorithms and models, and consideration of different effects from new technololy. Hardware/Software Codesign researches are focused on the HW/SW partitioning and design, whcih include the design of a tunable SOC platform, WLAN baseband, JPEG2000 and H.264. Analog IC design researches are focused on the design and implementation of RF circuits, D/A and A/D converters, clock and data recovery circuits.